The invention relates to controlling impedances of an integrated circuit.
Referring to FIG. 1, an integrated circuit chip, or package 10, typically includes a semiconductor die 17; pins, or leads 12; and a packaging material 3 that encapsulates the die 17 and holds the leads 12 in place. The core circuitry of the package 10 is fabricated in the semiconductor die 17, and the leads 12 form terminals for electrically connecting the circuitry on the die 17 with external circuitry.
Referring to FIG. 2, one way to make the package 10 includes mounting the die 17 on a center piece, or paddle 18, of an electrically conductive leadframe 11. Either a conductive or a nonconductive adhesive (e.g., an epoxy) may be used to secure the die 17 to the paddle 18. When a conductive adhesive is used, a dielectric layer may be placed between the die 17 and the paddle 18. During the initial stages of manufacture of the package 10, the leads 12 are an integral part of the leadframe 18 and extend inwardly toward the die 17.
To electrically connect the die 17 to the leads 12, bonding wires 14 are attached between the leads 12 and bond pads 15 of the die 17. One of the final steps of making the package 10 includes encapsulating the die 17 with the packaging material 3 which leaves a portion of the leads 12 exposed. After the encapsulation, the webbing of the leadframe 11 that connects the leads 12 together is cut away to electrically isolate the leads 12.
Referring to FIG. 3, another way to make an integrated circuit package 20 includes eliminating the bond wires 14 and alternatively mounting leads 22 of a different type of leadframe 26 directly to the die 17. Often called "tab bonding," the free ends of the leads 22 extend over the die 17 and mount directly to the bond pads 15 (shown in FIG. 3 by dotted lines). Besides establishing electrical connections with the die 17, the leads 22 also secure the die 17 to the leadframe 26. Regardless of whether the leads are directly mounted to the bond pads or mounted via bond wires, the extension of the leads over the die is often called a leads over chip (LOC) mounting scheme.
The different leads 12 are used for different purposes. For example, some of the leads 12 might be used to establish a ground connection, some might be used to carry supply voltages, and some might be used to connect circuitry on the die 17 to external components (e.g., a crystal or a large resistor) that are not fabricated on the die 17. Quite often, some of the leads 12, are used as I/O pins to transmit and receive data, control and address signals.
These I/O pins might be used to transmit and receive high frequency signals, such as, for example, signals that represent bits of data for a high speed memory device. At these high frequencies, even slight differences in the length of the bond wires 14 may cause the impedances present at the I/O pins to vary among the pins.
As an example of different bond wire lengths, a lead 12b (see FIG. 4) might be connected to a bond pad 15b (via a bond wire 14b) that is located near an edge (of the die 17) that is close to the lead 12b. However, a lead 12a that is adjacent to the lead 12b might be connected to a bond pad 15a (via a bond wire 14a) that is located near an opposite edge of the die 17. As a result, the impedances present at the two leads 12a and 12b are substantially different which can affect the performance of the package 10.